Zwischenpufferung von Daten und Log-Informationen im RTC slow memory des ESP32

Bee Observer BOB Entwicklung
25

Doesn’t work for me over a powercycle or a machine.reset() (but before/during same run-time). Returns empty (running FiPy v1.20.0.rc11).

26

“That memory is only persisted/restored after deep_sleep. It’s erased on reset.” – manningt

27

Yes, this will definitively only work for overcoming the deep sleep as outlined with RTC slow memory deep sleep demo above, while the device will still be powered solidly.

It will not protect against power outage or reset conditions.

28

Flash-based NVRAM for the win

What you probably want to use when talking about the FiPy without external NVRAM is the builtin one, which is actually a partition within the bulk of flash memory.

Using that, you will be able to persistently carry state across reboots or power cycles in all conditions, even after power loss. However, please be aware you should not apply a huge churn on it as everyone knows flash memory will die after a specific amount of read-/write cycles.

So, this memory area should not be used for buffering log data definitively yielding too much churn but might be suitable for humble buffering of measurement data if you know what you are doing.

Weitere Informationen dazu gibt es bei Per MicroPython Zeichenketten ins NVRAM des FiPy speichern.

2 Likes
29

Why is it 2 kB only while you can read on many pages (e.g.
ESP32 Deep Sleep with Arduino IDE and Wake Up Sources | Random Nerd Tutorials) :

With the ESP32, you can save data on the RTC memories. The ESP32 has 8kB SRAM on the RTC part, called RTC fast memory. The data saved here is not erased during deep sleep.

At least 4 kB should be addressable:

30

Increasing MEM_USER_MAXLEN to 6144 or even 4096 indeed does not work. The linker will croak as expected like outlined above.

AR build/FIPY/release/application.a
CPP build/FIPY/release/esp32_out.ld
LINK build/FIPY/release/application.elf
/path/to/xtensa/xtensa-esp32-elf/bin/ld: build/FIPY/release/application.elf section `.rtc.data' will not fit in region `rtc_slow_seg'
/path/to/xtensa/xtensa-esp32-elf/bin/ld: RTC_SLOW segment data does not fit.
collect2: error: ld returned 1 exit status

However, it will compile and link successfully when using 3840 (1024 * 3,75).

#define MEM_USER_MAXLEN     3840

I’ve confirmed this works:

>>> machine.RTC().memory('a' * 3840)
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